1. Field of the Invention
The present invention relates to a method for the production of a semiconductor wafer having a front and a back and an epitaxial layer of semiconductor material deposited on the front.
2. The Prior Art
According to the prior art, epitaxially grown semiconductor wafers are produced from suitable intermediate products by the process sequence of abrasive polishingxe2x80x94finish polishingxe2x80x94cleaningxe2x80x94epitaxy. The surface roughness after the abrasive polishing, is measured using the atomic force microscope (AFM) method in an area of 1 xcexcm by 1 xcexcm, being from about 0.5 to 3 nm RMS (root-mean-square), depending on the processing conditions, and being from about 0.05 to 0.2 nm RMS after the finish polishing.
EP 711 854 A1 describes a method for the production of an epitaxially grown wafer, in which a sawnxe2x80x94lappedxe2x80x94etched silicon wafer is abrasively polished. A surface roughness of from 0.3 to 1.2 nm RMS (AFM, 1 xcexcm by 1 xcexcm) is created and, to reduce costs, an epitaxial silicon layer is deposited without carrying out a smoothing finish polishing step. Although the epitaxy layer produced in this way is comparable, in terms of its electrical properties, with an epitaxy layer produced conventionally with prior use of a finish polishing step, there is a higher incidence of localized light scatterers (LLS) on the epitaxially grown surface. This is due to the relatively high initial roughness, and potentially leads to increased rejection of components produced on these wafers.
It is also known that defects in the substrate wafer, which can be detected as oxide precipitates, after the deposition of the epitaxial layer cause an increased number of localized light scatterers. EP-959154 A1 describes heat treatment of the substrate wafer, which precedes the epitaxial deposition and reduces the number of near-surface defects. It has been found, however, that the reduction which can be achieved in this way, especially when using substrate wafers in which a large number of such defects can be detected, is insufficient or entails high costs. The efficiency of the defect reduction depends on the length of the heat treatment. When the heat treatment is carried out only to an extent for which the associated costs remain at a tolerable level, an undesirably high number of localized light scatterers is found on the epitaxially grown surface.
It is an object of the present invention to provide a method which leads to an epitaxially grown semiconductor wafer that does not exhibit these disadvantages in terms of roughness and the number of localized light scatterers on the epitaxially grown surface, and which is also suitable for the use of semiconductor wafers having defects that can be detected as oxide precipitates.
Another object of the present invention is to provide a wafer in which the other properties of the epitaxially grown semiconductor wafer are at least as good as those of epitaxially grown semiconductor wafers produced according to the prior art.
The above objects are achieved according to the present invention which relates to a method for the production of a semiconductor wafer having a front and a back and an epitaxial layer of semiconductor material deposited on the front, which comprises the following process steps:
(a) preparing a substrate wafer having a polished front and a specific thickness;
(b) pretreating the front of the substrate wafer in the presence of HCl gas and a silane source at a temperature of from 950 to 1250 degrees Celsius in an epitaxy reactor, the thickness of the substrate wafer remaining substantially unchanged; and
(c) depositing the epitaxial layer on the front of the pretreated substrate wafer.
The method of the invention makes it possible to obtain a semiconductor wafer in which the surface of the epitaxial layer has a maximum density of 0.14 localized light scatterers per cm2 with a scattering cross section of greater than or equal to 0.12 xcexcm. Before the epitaxial layer is deposited, the front of the substrate wafer has a surface roughness of from 0.05 to 0.2 nm RMS, measured by AFM or a 1 xcexcm by 1 xcexcm large reference area. The semiconductor wafer is suitable for use in the semiconductor industry, especially for the fabrication of electronic components having linewidths equal to or less than 0.18 xcexcm.
Regarding step (a) of the process sequence according to the invention:
To produce the epitaxially grown semiconductor wafer according to the invention, a substrate wafer which, after separation from a crystal, has been, for example, lapped and etched or ground and etched or only ground, or is only in the sawn state. This substrate wafer is then subjected to an abrasive polish and optionally a finish polish finishing), the polish being carried out either on both sides at the same time or only on the front of the substrate wafer. A suitable polishing process for substrate wafers polished on two sides is described, for example, in DE-199 05 737 C1. The substrate wafer may be low in defects or affected by defects which can be detected as large near-surface oxide precipitates or as oxide-filled voids.
According to a preferred embodiment of the invention which, in particular, is preferred with regard to low costs, in step (a) of the method a substrate wafer having a polished front is prepared, for whose production only a single polishing step, i.e. an abrasive polish, is used. No finish polish is employed. The substrate wafer is removed from the polishing machine and is subjected to cleaning and drying according to the prior art. The cleaning may be implemented either as a batch method, with the simultaneous cleaning of a plurality of substrate wafers in baths, or by spraying methods, or alternatively as a single-wafer process.
According to a further, preferred embodiment of the invention, a polished substrate wafer is prepared in step (a) which is rich in defects that can be detected as large near-surface oxide precipitates or as oxide-filled voids. Such a substrate wafer lies within the scope of the invention if the density of defect seeds in at least one region of the substrate wafer, according to OSF testing (conditions: wet oxidation at 1100xc2x0 C. for 2 hours with subsequent Secco treatment for 3 minutes (doping: pxe2x88x92) or wet oxidation at 1100xc2x0 C. for 2 hours with subsequent Wright treatment for 3 minutes (doping: p+)), reaches a value of least 5/cm2 (near-surface oxide precipitates) or, after 20 min of non-shaken Secco treatment, at least 2 xcexcm large Secco etch pits and/or large pits with a density of at least 0.05/cm2 (oxide-filled voids) are found in the void-rich region of the wafer. This is generally the case if the oxygen concentration is in the range of from 3*1017 to 9*1017 atoms of oxygen cmxe2x88x923, preferably from 5*1017 to 7.5*1017 atoms of oxygen cmxe2x88x923, and the concentration is determined according to the American ASTM standard, and at least one of the following conditions is satisfied with respect to dopants and their concentrations in the substrate wafer.
The nitrogen concentration is in the range of from 1*1010 to 5*1015 atoms of nitrogen cmxe2x88x923, preferably from 5*1012 to 5*1015 atoms of nitrogen cmxe2x88x923. The carbon concentration is in the range of from 1*1015 to 5*1017 atoms of carbon cmxe2x88x923, preferably from 1*1016 to 5*1017 atoms of carbon cmxe2x88x923. The boron concentration is in the range of more than 5*1017 atoms of boron cmxe2x88x923. The described category of substrate wafers affected by defects includes, in particular, silicon wafers on which an annular buildup of defect seeds, a so-called OSLO ring, car be A detected (OSF=oxidation induced stacking fault) and silicon wafers which have a high density of oxide-filled voids in the crystal (M. Hourai et al. in The Electrochem. Soc. PV98-1 (1998), page 453 and G. Kissinger et al. in Appl. Phys. Lett. (1998), page 223).
The substrate wafer affected by defects can also have been prepared in an only abrasively polished state, or may also be subjected to a finish polish in addition to an abrasive polish.
Regarding step (b) of the process sequence according to the invention:
The polished surface of the front of the substrate wafer is conditioned during step (b) of the method so that the quality of the subsequently grown epitaxial layer achieves the above mentioned object, with regard to the maximum number of localized light scatterers on the surface. Surprisingly, this is achieved in that the substrate wafer in step (b) of the method, preferably a silicon wafer, is treated in the presence of HCl gas and a silane source at a temperature of from 950 to 1250 degrees Celsius, preferably from 1050 to 1150 degrees Celsius, in an epitaxy reactor. The concentration of the HCl gas and of the silane source is adjusted so that essentially neither deposition of silicon nor etching erosion of semiconductor material takes place. Thus the thickness of the semiconductor wafer is not substantially changed. Some departure from the equilibrium state can be tolerated. The tolerable range is between at most 0.5 xcexcm/min for deposition and at most 0.2 xcexcm/min for etching erosion. Also included, in terms of the thickness of the substrate wafer, is a thickness reduction of up to 0.5 xcexcm, preferably up to 0.2 xcexcm, or a thickness increase of up to 0.5 xcexcm. preferably up to 0.2 xcexcm.
The etching and deposition take place with a sufficiently high reaction rate, so that the silicon on the surface is quasi-mobile and smoothing of the surface and removal of defects on the surface occur. In addition to HCl gas and the silane source, which is a gas, the atmosphere may also contain a doping gas. This is preferred, in particular, if the pretreatment is carried out under conditions with which material is deposited to the tolerable extent. A defect-free, smoothed monocrystalline silicon surface is obtained after the pretreatment. The literature describes that HCl in a hydrogen atmosphere exerts an etching and smoothing effect on a silicon surface (H. M. Liaw and J. W. Rose in: Epitaxial Silicon Technology, Academic Press Inc., Orlando Fla. 1986, pages 71-73 and M. L. Hammond in Handbook of Thin-Film Deposition Processes and Techniques, Noyes publications 1988, pages 32 and 33). It has now been found, surprisingly, that the additional presence of a silane source can significantly improve and accelerate the smoothing of the surface and the removal of crystal defects.
It is particularly preferred to remove native oxide from the front of the substrate wafer in a first sub-step, preferably by exposing the substrate wafer to a pure hydrogen atmosphere at a temperature of from 900 to 1200 degrees Celsius, preferably at a temperature of from 1100 to 1150 degrees Celsius, in a reactor which is also used for the subsequent epitaxial deposition of a silicon layer. The native oxide can, however, also be removed in another known way, for example by treating the substrate wafer with hydrogen fluoride. The pretreatment according to step (b) is then carried out in a second sub-step, preferably by introducing a mixture comprising a silane source, which is a gas, HCl gas and hydrogen into the epitaxy reactor. If native oxide has previously been removed using hydrogen, it is sufficient to add the silane source which is a gas, and HCl to the hydrogen atmosphere which is already present.
Particular examples of suitable silane sources include silane (SiH4), dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), tetrachlorosilane (SiCl4) or a mixture of these substances, each of which is a gas under the reaction conditions. Trichlorosilane is especially preferred.
Regarding step (c) of the process sequence according to the invention:
In the last step of the process sequence, the substrate wafer obtained by the treatment according to step (b) is provided with an epitaxial layer on at least the front by a standard method. This is done using a CVD (chemical vapor deposition) method, preferably with silane (SiH4), dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), tetrachlorosilane (SiCl4) or a mixture of these substances being delivered to the wafer surface. Here they are decomposed at temperatures of from 600xc2x0 C. to 1250xc2x0 C. into elemental silicon and volatile byproducts. They form an epitaxial silicon layer, i.e. a monocrystalline silicon layer grown crystallographically oriented with the semiconductor wafer. Silicon layers having a thickness of from 0.3 xcexcm to 10 xcexcm are preferred. The epitaxy layer may be undoped or deliberately doped, for example with boron, phosphorus, arsenic or antimony, in order to establish the conduction type and the desired conductivity.
After the process sequences (a) to (c) according to the invention have been carried out, an epitaxially grown semiconductor wafer having a haze-free surface is provided. This wafer may be sent for characterization of its properties before it is processed further to produce semiconductor components. Measurements using an optical surface inspection instrument working on the laser basis show maximum density of 0.14 localized light scatterers per cm2 of epitaxially grown silicon surface, and a surface roughness (haze) of less than 0.2 ppm and a microroughness of  less than 1 nm RMS.
An epitaxially grown semiconductor wafer produced according to the invention, in particular a silicon wafer having an epitaxial silicon coating, meets the requirements for the production of semiconductor components having linewidths equal to or less than 0.18 xcexcm. The method according to the invention has proved to be an optimal solution for the production of epitaxially grown silicon wafers having the described features. It obviates cost-intensive steps for local geometry correction such as, for example, plasma etching. Finish polishing is also not necessarily required. Due to the low number of process steps, the risk of fracture is also reduced.
Other objects and features of the present invention will be come apparent from the following detailed description considered in connection with the accompanying Examples which disclose several embodiments of the present invention. It should be understood, however, that the Examples are designed for the purpose of illustration only and not as a definition of the limits of the invention.